// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_rtsq_s_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:25:27 Create file
// ******************************************************************************

#ifndef __STARS_RTSQ_S_REG_REG_OFFSET_FIELD_H__
#define __STARS_RTSQ_S_REG_REG_OFFSET_FIELD_H__

#define STARS_RTSQ_S_REG_VFG_SEC_LEN    1
#define STARS_RTSQ_S_REG_VFG_SEC_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_0_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_0_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_1_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_1_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_2_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_2_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_3_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_3_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_4_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_4_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_5_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_5_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_6_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_6_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_7_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_7_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_8_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_8_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_9_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_9_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_10_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_10_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_11_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_11_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_12_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_12_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_13_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_13_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_14_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_14_OFFSET 0

#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_15_LEN    32
#define STARS_RTSQ_S_REG_STARS_SQ_SEC_EN_15_OFFSET 0

#define STARS_RTSQ_S_REG_NS_SQ_ARPROT_SWAPBUF_LEN    3
#define STARS_RTSQ_S_REG_NS_SQ_ARPROT_SWAPBUF_OFFSET 16

#define STARS_RTSQ_S_REG_S_SQ_ARPROT_SWAPBUF_LEN    3
#define STARS_RTSQ_S_REG_S_SQ_ARPROT_SWAPBUF_OFFSET 16

#define STARS_RTSQ_S_REG_ARNS_SWAPBUF_LEN    1
#define STARS_RTSQ_S_REG_ARNS_SWAPBUF_OFFSET 16

#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_SDMA_S_LEN             5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_SDMA_S_OFFSET          24
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_FFTS_AIV_ONLY_S_LEN    5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_FFTS_AIV_ONLY_S_OFFSET 16
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_PCIEDMA_S_LEN          5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_PCIEDMA_S_OFFSET       8
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_FFTS_S_LEN             5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_FFTS_S_OFFSET          0

#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_DSA_S_LEN      5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_DSA_S_OFFSET   24
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_JPEGE_S_LEN    5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_JPEGE_S_OFFSET 16
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_JPEGD_S_LEN    5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_JPEGD_S_OFFSET 8
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_VPC_S_LEN      5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_VPC_S_OFFSET   0

#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_FFTS_AIC_ONLY_S_LEN    5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_FFTS_AIC_ONLY_S_OFFSET 24
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_MBLK_CPU_S_LEN         5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_MBLK_CPU_S_OFFSET      16
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_SBLK_CPU_S_LEN         5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_SBLK_CPU_S_OFFSET      8
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_CONDS_S_LEN            5
#define STARS_RTSQ_S_REG_RTSQ_SWAPIN_MAX_CONDS_S_OFFSET         0

#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_BASE_ADDR_L_LEN    32
#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_BASE_ADDR_L_OFFSET 0

#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_IS_VIRTUAL_LEN     1
#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_IS_VIRTUAL_OFFSET  31
#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_SHIFT_LEN          6
#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_SHIFT_OFFSET       17
#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_BASE_ADDR_H_LEN    17
#define STARS_RTSQ_S_REG_S_SQ_SWAP_BUF_BASE_ADDR_H_OFFSET 0

#endif // __STARS_RTSQ_S_REG_REG_OFFSET_FIELD_H__
